Category Archives: IBM Mainframe Assembler

In the last post I suggested we take the challenge that John Ehrman posed in problem 41.7.1 of his well-known and used assembler book:

Programming Problem 41.3.(3)+ Write a program with a program interruption exit that generates each of the 15 possible interruption types in turn. For each interruption, generate a message describing the interruption type and the address of the interrupted instruction. Then, return to the mainline program to generate the next interruption.

David Staudacher contributed a number of interesting ways to abend, but I especially liked BCTR R15,R15 for a protection exception. Melvyn Maltz had some interesting comments about the whole issue and suggested he gets S0C5s whenever he uses a bad index into a branch table. You can see all their contributions in the comments on the last article.

I was surprised (after posting) to discover that John himself had already weighed in on this challenge in the Solutions part of his book. Here is what he published (page 1275 of his book):

41.7.1. Some possible but unverified instruction sequences are:

(01)  DC H’0′ Invalid operation

(02)   LPSW 0,8(0,0) Privileged operation

(03)  EX 0,* Execute

(04)  MVI 0,0 Protection

(05)  LGHI 1,-1

IC 1,0(,1) Addressing

(06)   DC X’1D11′ DR 1,1: Specification

(07)  AP *,* Decimal Data

(08)  LA 1,1

SLA 1,33 Fixed-point overflow

(09)   SRDL 0,63

DR 0,0 Fixed-point divide

(0A)   AP A,A Decimal Overflow

A DC P’6′

(0B)   DP A,=P’0′ Decimal Divide

(0C)   LE 0,=E’1E72′ Exponent overflow

MER 0,0

(0D)  LE 0,=E’1E-72′ Exponent underflow

MER 0,0

(0E) LE 0,=X’41000001′ Significance

SU 0,=X’41000001′

(0F)  LE 0,=E’1′ Floating-pointdivide

D 0,=E’0′

I tried running the code above and found an assembly error on (02). John said the code suggestions were unverified! Still he was on the right track. LPSW is a type S instruction and expects a simple base/displacement address, so LPSW 0(8) will generate the error he intended.

You can also get away with SLA 1,32 on (08), but that’s nit-picking.

The only problem in the list was his suggestion for (05) which generated an S0C6 for me instead of the S0C5 we require.

So how do we get a S0C5 exception to occur? I’ve tried a number of bad branches – protection errors every one. After reading the Principles of Operation, I’m wondering if a garden-variety programmer can easily get a S0C5? I hope one of you will prove me wrong. Send me the code that generates a S0C5!

If you would like to pursue on-line assembler training with me starting Fall, 2019, check out the Marist University IDCP program here:  http://idcp.marist.edu/enterprisesystemseducation/zosprogramoverview.html

You can explore their main website here: http://idcp.marist.edu/

 

I have been away from the website for quite a while, but I’m trying to get back to it again.  Over the past year, I’ve been busy writing a novel (mystery), and I also added a second grandson this year. And of course, there’s golf to play.

If you are looking for online assembler training or other z/OS training, you might consider the Marist College Institute for Data Center Professionals (IDCP) program.  The program starts in late August and there will be an online assembler course starting in December. I have taught the assembler course over the last few years.  They have also added a security certificate. Here is a link to the Marist site:  Marist IDCP

I cut the following graphic from their latest blurb which describes the programs they offer.

 

Learn one new instruction today – Compare and Branch – CRB.  You can tighten your code just a bit with CRB, an instruction that combines a comparison operation on two registers with a branch operation – all in one line.  It comes with some extended mnemonics that make it easy to use.  Learn all about it here in the time it takes to finish a cup of coffee.

I envisioned VisibleZ as a teaching tool for assembly language – I wanted to force students to deal with object code as a way to learn the assembly language. With VisibleZ, after writing a few bytes of object code, you can watch the effects of a given instruction on the state of the machine, and in the process learn a thing or two.  Or, you can simply step through the hundreds of pre-written program snippets that comes with it.  I’ve tried to make it easy to write program snippets – two hex characters represent a byte, with bytes separated by spaces – all in a text file. No need to write a large program to get some experience with an instruction.

A few months ago, James Cray, one of the contributors to  z390, the Portable Assembler and Emulator Project , suggested it would be nice to be able to load z390 object modules into VisibleZ.  If you’re not familiar with that project, and you don’t have access to a mainframe, you should check it out.  Using z390 you can write large, well-developed assembler programs and run them on your pc.  It also supports Cobol and CICS!

I didn’t want to want to change my original file format, but I decided to take James’ advice by providing some support for z390.  I’ve just posted an experimental version (executable jar / codes.zip -code snippets) of VisibleZ that will take the assembler listings produced by z390 and scrape off the object code and format it it to run in VisibleZ.  You will have to install z390 separately and tell VisibleZ where it lives on your machine.  After that you can assemble a program and run your program, all within VisibleZ.

The experimental version runs on Windows only.  If there is any interest in getting this to run on Linux, let me know.  I’ll remind you that VisibleZ still has limited support for QSAM files – 80 byte records and a limit of three input and three output files.