VisualZ Update 5/17/2016

I’ve updated the RunnerB.jar file for VisualZ.  Replacing your copy of RunnerB.jar with this one will give you the most up-to-date version of VisibleZ.   This update fixes a problem with condition code settings that occurred in some cases for A, AH, S, and SH.  This version also includes many new immediate arithmetic instructions.   LARL was also added to the instruction set.  You should also download, upzip it, and replace your Codes directory with this one.  The new Codes directory contains sample programs for each of the new instructions that was added.

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Visual Prompts for Grande Arithmetic

Can’t remember all the details of the Divide Single Grande Fullword Register instruction (DSGFR)?  Not sure of the set up for Multiply Single (MS)?  Consulting Principles of Operation for the umpteenth time today?  You can quickly learn (or review) 21 grande arithmetic instructions using the visual clues I’ve provided on four new pages (pdf). Check out the pages below and leave the POPS manual for the hard stuff.

Additionally, I’ve added a video to explain the visual clue sheets and exactly how these instructions work:

All of these items have been added to the video course.

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Jumping Into Branches

Are you bewildered by the plethora of branch instructions in assembly language?  Perhaps you’re wondering what all that jumping around is about?  Not sure when to choose JNE over BNE or BC?  This new paper addresses those issues and a few more you might find helpful.  I’ll give you my own take on how to decide when to jump and when to branch.  You might also learn a new way to load base registers, get a grip on relative branching, or improve your understanding of addressability.  Click here for the pdf and jump in!

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Elegant Machine Code:

“The Happy Mainframe” or “WWzD: What Would z Do?”

I am happy to welcome David Staudacher, who begins a series of blogs about solving problems with elegant, succinct assembler code – code that System z itself would write (if it could).  David has been writing Mainframe code in Assembler and COBOL for over 35 years,  in both vendor software and business application environments.  He is currently employed with the State Employees’ Credit Union of North Carolina  and co-manages the “Mainframe Assembler Professionals” and  “Mainframe [COBOL, etc] Experts” Groups on LinkedIn.

Problem: Read Error on Newly Allocated, Empty Sequential Disk Files


//SYSIN    DD *

NEWFL       00      4
REPRO       12     24

IEC141I 013-34,IGG0191I,,,INFILE – IEC141I

Basically, there’s no EOF mark and no DCB information in the DSCB because the file was never OPENed for Output, even though RECFM and LRECL were specified in the JCL.

Essential Solution: A program to use with file allocation (rather than IEFBR14), sufficient just to Open and Close the file, thus creating a valid and usable DSCB.

Using this OPEN/CLOSE program instead of IEFBR14 …

// EXEC PGM=PSINIT “PSINIT” = (P)hysical (S)equential (INIT)ialization
//SYSIN    DD *

… now everything is hunky-dory:

NEWFL       00      9
REPRO       00     26

This is an excellent opportunity to “make the Mainframe happy” with some “elegant machine code” written in Assembler!

The essential solution can be accomplished with as little as one DCB, six machine instructions and a fullword aligned 4-byte Parameter List (DCB pointer with option bits in the high-order byte):


Note: The DCB here specifies “MACRF=W”, which makes this a BSAM DCB.

A QSAM DCB (MACRF=PM or PL) would work just as well, but since we only need OPEN and CLOSE, simple BSAM works just fine.

The DDNAME parameter (here = “NEWFILE”) must also match the DDNAME used in the JCL.

(2)    The fullword-aligned Parameter List (in 4 contiguous bytes) is:

  • Fullword Alignment: DC 0F’0’
  • Option Bits:  DC X’8F’ (see “Bit Settings for OPEN (SVC 19) and Bit settings for CLOSE (SVC 20)” below for bit meanings)
  • DCB Pointer: DC AL3(DCB)From “MVS Diagnosis Reference” (GA22-7588), the relevant option byte bit settings for the necessary OPEN (SVC 19) and CLOSE (SVC 20) in this case are:
    Bit Settings for OPEN (SVC 19) Bit Settings for CLOSE (SVC 20)
    1... .... = Last entry indicator
    .... 1111 = OUTPUT
    1... .... = Last entry indicator

    Notice how there is no overlap using these particular bit settings.   Thus, the same Parameter List can be used forboth OPEN and CLOSE.

(3)    The Six Machine Instructions are:

  1.   X’4120bddd’– Load R2 with the Address of the Parameter List (’bddd’is the Base+Displacement Parameter List address, determined at assembly time).Note: Loading R1 would be sufficient, but subsequent SVC 19 modifies R1 so the less volatile R2 is used instead so address can be easily reloaded for CLOSE (SVC 20).
  2. X’1812’ – Load R1 with address of required Parameter List for SVC 19 (OPEN).
  3. X’0A13’ – Issue SVC 19 (OPEN).
  4. X’1812’ – Reload R1 with address of required Parameter List for SVC 20 (CLOSE).
  5. X’0A14’ – Issue SVC 20 (CLOSE).
  6. X’07FE’ – BR 14

This solution, unlike most written in so-called “high level” languages,  will work with any sequential disk file, of any valid record length and any Record Format.

Specific and essential DCB information, like RECFM, LRECL and BLKSIZE, are obtained via JCL and SMS defaults rather than hardcoded in the program.  Nice!

Here’s the Assembly ready code then, exactly as the machine might write it, with:

(1)    A “USING” on R15 (R15 = Base) since the machine “knows” R15 contains the Entry address at runtime.

(2)    A label “PLIST” on the Parameter List, giving the displacement so the address can be calculated at runtime.

(3)    A label “DCB” on the DCB, so “AL3(DCB)” will contain the DCB address at runtime.

       USING PSINIT,15     R15 = BASE
       LA     2,PLIST      R2 -> PARMLIST
       LR     1,2          R1 -> PARMLIST
       SVC    19           ISSUE OPEN SVC
       LR     1,2          R1 -> PARMLIST
       SVC    20           ISSUE CLOSE DCB
       BR     14           RETURN
PLIST  DC     0F’0’,X'8F',AL3(DCB)

Knowing the machine code generated by the “MF=E” forms of the OPEN and CLOSE macros, and the “MF=L” form of OPEN, the Assembly code can be simplified even further to just 9 statements…

       USING PSINIT,15    R15 = BASE
       LA    2,PLIST      R2 -> PARMLIST
       OPEN  MF=(E,(2))   OPEN FILE
       CLOSE MF=(E,(2))   CLOSE FILE
       BR    14           RETURN
       END   PSINIT

… which generate exactly the same load module.

– “OPEN MF=(E,(2))” generates “LR 1,2” and “SVC 19”.

– “CLOSE MF=(E,(2))” generates “LR 1,2” and “SVC 20”.

– “OPEN MF=L,(DCB,OUTPUT)” generates “DC 0F’0’”, “AL1(143)” and “AL3(DCB)”.  (note: “AL1(143)” = “X'8F'”)

NEXT: The same solution using AMODE 31 with an external DCB module, loaded dynamically at runtime.


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Joe Goes Small (< 4k)

Joe Developer had an astute comment about “Lots of Code on One Base Register” when he reminded me that lots of long programs have been written that use one base register, and without resorting to relative branches. By modularizing the program into sections of < 4k, you can write as much code as you like on one base register. There are some real benefits in his reminders. When designing programs, small is always a beautiful way to think. I thought it might be helpful to have an example program that illustrates the ideas. I’ve placed a copy of it here.
At 13k+, you have to admit it’s relatively long for a program that doesn’t do much of anything. I threw in a few odds and ends to illustrate some related ideas and concepts that might be of interest to someone learning assembler. Let me point out a few:

  1. The program is one source module organized into four control sections.
  2. Each control section can call the others. In this case, MAIN1 calls SUBR1 and SUBR2, and SUBR2 calls SUBR3.
  3. MAIN1 uses the CALL macro and passes parameters.
  4. SUBR2 invokes SUBR3 and passes parameters without using a CALL.
  5. SUBR1 illustrates passing parameters by content and by reference.
  6. MAIN1 passes a DCB which is used in SUBR1.
  7. Each routine is < 4k and uses standard linkage techniques (save and restore registers in save areas, parameter passing).
  8. Each routine uses a single base register.
  9. Each routine avoids the use of relative branching (although this would be fine, too).
  10. We could easily add more routines and make this arbitrarily large.
  11. Passing large amounts of data could be handled with different techniques.

There are other ways to write large programs and perhaps Joe had a different idea in mind, but I think this is close to what he was driving at.  And as Joe points out, 4k is not much of a constraint in most cases.  You can write a lot of assembler code in a 4k space – plenty of room for most well-designed modules.

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VisibleZ Academic Paper

Some  colleagues and I recently published an academic article about VisibleZ in a Bulgarian computing journal.  If the journal releases the article, I will post it on the site.  For the record, here are the details:

David Woolbright, Vladimir Zanev, Neal Rogers, “VisibleZ:  A Mainframe Architecture Emulator for Computing Education”, Serdica Journal of Computing-Volume 8, No 4, 2015.

I’m still cleaning things up and repairing some broken links on the assembler site as well as my academic site.  I’ve about got them under control again after my sites went through a major server move at school.

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BRC and BRCL Instruction Lessons

I’ve added lessons on two relative branch operands that have become fundamental tools for “baseless” programs:  Branch Relative on Condition and Branch Relative on Condition Long.  You can try out these instructions in VisibleZ as well.  Upload the new Codes directory for some sample object code programs, or build your own.

Along with these lessons, I cleaned up some links on the assembler page and added links to all the lessons in three formats (PDF, DOCX, HTM).

I’m working on an assembler book that will organize and combine the information you can find on the site.  I hope to complete it over the next few months.  If you have special requests for topics you would like me to include, email me your suggestions.  I’d like to know the instructions you’re using that aren’t represented here.


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