In the last post I suggested we take the challenge that John Ehrman posed in problem 41.7.1 of his well-known and used assembler book:
Programming Problem 41.3.(3)+ Write a program with a program interruption exit that generates each of the 15 possible interruption types in turn. For each interruption, generate a message describing the interruption type and the address of the interrupted instruction. Then, return to the mainline program to generate the next interruption.
David Staudacher contributed a number of interesting ways to abend, but I especially liked BCTR R15,R15 for a protection exception. Melvyn Maltz had some interesting comments about the whole issue and suggested he gets S0C5s whenever he uses a bad index into a branch table. You can see all their contributions in the comments on the last article.
I was surprised (after posting) to discover that John himself had already weighed in on this challenge in the Solutions part of his book. Here is what he published (page 1275 of his book):
41.7.1. Some possible but unverified instruction sequences are:
(01) DC H’0′ Invalid operation
(02) LPSW 0,8(0,0) Privileged operation
(03) EX 0,* Execute
(04) MVI 0,0 Protection
(05) LGHI 1,-1
IC 1,0(,1) Addressing
(06) DC X’1D11′ DR 1,1: Specification
(07) AP *,* Decimal Data
(08) LA 1,1
SLA 1,33 Fixed-point overflow
(09) SRDL 0,63
DR 0,0 Fixed-point divide
(0A) AP A,A Decimal Overflow
A DC P’6′
(0B) DP A,=P’0′ Decimal Divide
(0C) LE 0,=E’1E72′ Exponent overflow
MER 0,0
(0D) LE 0,=E’1E-72′ Exponent underflow
MER 0,0
(0E) LE 0,=X’41000001′ Significance
SU 0,=X’41000001′
(0F) LE 0,=E’1′ Floating-pointdivide
D 0,=E’0′
I tried running the code above and found an assembly error on (02). John said the code suggestions were unverified! Still he was on the right track. LPSW is a type S instruction and expects a simple base/displacement address, so LPSW 0(8) will generate the error he intended.
You can also get away with SLA 1,32 on (08), but that’s nit-picking.
The only problem in the list was his suggestion for (05) which generated an S0C6 for me instead of the S0C5 we require.
So how do we get a S0C5 exception to occur? I’ve tried a number of bad branches – protection errors every one. After reading the Principles of Operation, I’m wondering if a garden-variety programmer can easily get a S0C5? I hope one of you will prove me wrong. Send me the code that generates a S0C5!